1. Field of the Invention
The present invention relates to interconnects for surfing circuits.
2. Related Art
With growing chip sizes and operating frequencies, the on-chip global interconnect has become a critical performance bottleneck for CMOS technology. More specifically, as process technologies move to deep submicron feature sizes, transistor delays continue to decrease. However, interconnect delays are not following the same trend. For example, FIG. 2 shows an exemplary delay trend for global interconnects in microprocessors. Note that the gap between the interconnect delay and the fan-out-of-four inverter delay (FO4 delay), continues to increase. Buffers can be inserted into the interconnect to reduce the delay, and a substantially minimal delay can be achieved when wire delay matches buffer delay and when wire capacitance matches buffer capacitance. Because power consumption grows linearly with total capacitance, inserting buffers into the interconnect to reduce the delay of the interconnect has the undesirable effect of increasing the power consumption of the interconnect. While this increase in power consumption can be reduced by sizing buffers and wires to minimize the energy-delay product, power consumption remains a critical issue for long-wire interconnects.
Increasing the bandwidth of the interconnect is desirable to improve system performance. However, bandwidth is limited by timing variations caused by skew and jitter. Timing variations are a function of temperature variation, crosstalk noise, power supply variation, and parameter variation, and timing variations increase with the length of global interconnect lines. Moreover, jitter and skew in clock signal for a transmitter and a receiver add timing variation to on-chip interconnect communications.
The total timing uncertainty limits the bandwidth of the system. To reduce the timing uncertainty of the global interconnect, substantial effort have been invested into reducing clock skew and jitter. Unfortunately, this can lead to a complex clock network with high power consumption. One solution to this problem is to insert latches in place of some of the buffers to control the timing variation. However, these latches increase latency and consume extra power.
Hence, what is needed is an interconnect for surfing circuits without the above mentioned problems.